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Preliminary
1/2 1/3 1/4 Duty LCD Driver
! GENERAL DESCRIPTION
NJU6543 is a 1/2 or 1/3,1/4 duty segment type LCD driver. It incorporates 4 common driver circuits and 128 segment driver circuits. NJU6543 can drive maximum 256 segments in 1/2 duty ratio and maximum 384 segments in 1/3 duty ratio and maximum 512 segments in 1/4 duty ratio. In addition, the NJU6543's useful functions meet a wide
NJU6543
! PACKAGE OUTLINE
range of applications.
NJU6543
! FEATURES
# LCD driving circuit :Max. 128outputs (4 outputs as for general purpose ports) # Programmable Duty Ratio 1/2 Duty Ratio :Driving max. 256 segments 1/3 Duty Ratio :Driving max. 384 segments 1/4 Duty Ratio :Driving max. 512 segments # Programmable Bias Ratio :1/2, 1/3 bias ratio # Electrical Variable Resistance :8-steps # Serial Data Transfer :Shift clock max. 2MHz # Built-in Oscillator :CR oscillation with external resistor and capacitance, or external oscillation
signal input
# Operating Voltage # C-MOS Technology # Package Outline :3.0V / 5.0V :P-Sub :LQFP144 20mm*20mm t=1.7mm(max) Pin-pitch=0.5mm
! BLOCK DIAGRAM
COM1 VDD V0 COM4 SEG1 SEG8 SEG9 SEG16 SEG17 SEG24 SEG121 SEG125/P1 SEG128/P4
EVR
V1 V2 V3 VSS TEST OSC
COM Drivers
//
Segment Drivers /General Purpose Output Ports
//
Data Latch Circuit
Oscillator
Display Data Register
CSb SCK SI RSTb
Decoder
Command Register
Power ON Reset Circuit
Ver.2008-11-28
-1-
NJU6543
! PIN CONFIGURATION
* LQFP144 SEG104
Preliminary
104
102 101
108
106 105
107
103
100 99 98 97 96
94 93 92
85 84
91
90 89 88
87 86
83
82 81
80
79 78
77
76
75 74
95
73 72 71 70 69 68 67 65 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 SEG32 36
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
SEG105
SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57
NJU6543
SEG124 SEG125/P1 SEG126/P2 SEG127/P3 SEG128/P4 V0 V1 V2 V3 VSS OSC TEST RSTb CSb SI SCK VDD 24 25 33 17 18 19 20 21 SEG4 8 SEG5 9 SEG6 10 SEG7 11 SEG8 12 SEG9 13 SEG10 14 15 16 22 23 26 27 28 29 30 31 32 SEG33 34 35
1
2
3 4 SEG1 5
COM1 COM2 COM3 COM4
SEG2 6 SEG3 7
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Ver.2008-11-28
SEG69
Preliminary
! TERMINAL DISCRIPTION
No. 144 133 134 135 136 137 139 Pad Name VDD V0 V1 V2 V3 VSS TEST Function
NJU6543
Power supply: 3V /5V LCD driving voltage
V0 V1 V2 V3 VSS, V0 VDD
Bias At 1/3 bias ratio, keep V2- V3 open. At 1/2 bias ratio, short V2- V3. GND VSS =0V TEST Keep TEST-VSS short Reset When RSTb is "L", command register and latch circuit is reset. When this terminal is not used, should be VDD short. (keep power supply condition when hardware reset circuit is used) Chip select When CSb is "L", data can be read in. Serial data input (8 bit=1word) Serial clock External resistor and capacitance connection terminal for CR oscillation, or external clock input terminal Common driver outputs Segment driver outputs Segment driver outputs/general purpose output ports These 4 terminals can be used as segment outputs or general purpose output ports by setting Command Register. When selected as general purpose ports, data can be outputted via these ports during COM1 timing. According to transferred data, "H"=VDD or "L"=VSS will be outputted.
140
RSTb
141 142 143 138 1~4 5~128
CSb SI SCK OSC COM1 ~ COM4 SEG1 ~ SEG124
129~132
SEG125/P1 ~ SEG128/P4
Ver.2008-11-28
-3-
NJU6543
Preliminary
! FUNCTION DESCRIPTION
(1) Block Function * Oscillator The oscillator includes an external capacitor and an resistor. When use external clock, input the clock signal to OSC.
*
It generates clock signal for LCD driving.
Decoder Input serial data is decoded and sent to the appropriate block. Command Register Command data is written to this 8 bits command register to control NJU6543 operation. Display Data Register Data is written to this 8 bits register as display data. Latch Circuit Data stored in display data register is assigned to the corresponding SEG/port. Segment Driver/General Purpose Ports Basing on display data, segment drivers output LCD SEG driving signal. And, SEG125/P1 ~ SEG128/P4 terminals can be selected as segment driver output or general-purpose ports by instruction. Common Driver Common drivers output LCD COM driving signal. Power On Reset When power is on, NJU6543 is automatically initialized. And if RSTb="L", NJU6543 is reset too. Electrical Variable Resistance (E.V.R.) The Electrical Variable Resistance adjusts LCD Driving Voltage from V1 to V3.
*
*
*
*
*
*
*
-4-
Ver.2008-11-28
Preliminary
NJU6543
During
(2) Serial Data Transfer The transfer of an 8-bit/word serial data is conducted by synchronizing clock via interface with CPU. CSb="L", serial data is obtainable and will be read in at the rising edge of SCK signal.
After CSb becoming low, by the first word, address data is distinguished by D7 and D6. In the case of address data(D7,D6="0,1"), the 2nd data can be transferred continually and interrupted as display data even if CSb maintained low. In this case, every 8-bits data will be confirmed as a word either by th the falling edge of the8 SCK clock or by the rising edge of the CSb clock. After CSb becoming low, if the first word is command data(D7,D6="1,0"or "1,1"), the after data is invalid even though transfer can be continued without changing the polarity of CSb.( Effective the first word) At the falling edge of CSb, SCK can be either "H" or "L", but, at the rising edge of CSb, SCK must be low.
At this rising edge, one word is confirmed Command data CSb
SCK
SI
D7
D6
D5
D4
D3
D2
D1
D0
Timing of Serial Data Transfer SCK and SI (Address data and display data) At this rising edge of CSb, SCK="Lo", one word is confirmed. when
CSb
SCK
WORD 1 WORD2 WORD n
SI
Serial Interface Format
Ver.2008-11-28
-5-
NJU6543
Preliminary
(3) Command Register1 Command Register1 is used to set the duty ratio, the bias ratio, and the SEG driver/general purpose ports. st When the D7 to D6 bits of the 1 word are (1,0), the D5 ~ D0 bits are recognized as command data. The contents of Command Register will be initialized as following when applying Power On Reset or Reset. The Default Value of Command Register * Duty ratio * Bias ratio * SEG driver/General purpose ports D7 1 D6 0 D5 DS1 D4 DS0
: 1/4 : 1/3 : SEG drivers(SEG125,SEG126, SEG127, SEG128) D3 BS D2 TSEL2 D1 TSEL1 D0 TSEL0
Flag bits
*
Duty ratio
Bias ratio
SEG driver or general purpose ports
Duty ratio DS1 DS0 Duty ratio 0 0 1/4 0 1 1/3 1 0 1/2 *) Do not change the duty ratio during display ON. **) If DS1 and DS0 are set as (1, 1), it set as the same 1/4Duty as (0, 0).
*
Bias ratio BS 0 1 Bias ratio 1/3 1/2
*
SEG driver or general purpose ports TSEL2 TSEL1 TSEL0 SEG125/P1 SEG126/P2 SEG127/P3 SEG128/P4 0 0 0 SEG125 SEG126 SEG127 SEG128 0 0 1 SEG125 SEG126 SEG127 P4 0 1 0 SEG125 SEG126 P3 P4 0 1 1 SEG125 P2 P3 P4 1 0 0 P1 P2 P3 P4 ***) If TSEL2 ~ TSEL0 is set to (1, 0, 1), (1, 1, 0), (1, 1, 1) all outputs are used as segment drivers.
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Ver.2008-11-28
Preliminary
NJU6543
(4) Command Register2 * Command Register2 is used to set the oscillator, driving waveform, and E.V.R. resister set. When the D7 to D6 st bits of the 1 word are (1,1), the D5 ~ D0 bits are recognized as command data. The contents of Command Register will be initialized as following when applying Power On Reset or Reset. The Default Value of Command Register * Oscillator selection * Driving waveform * E.V.R. Register Set * Display D7 1 D6 0 D5 EXOSC D4 WSEL
: External resistor and capacitor : A(Time sharing system frequency) waveform : V0(0,0,0) :OFF D3 E2 D2 E1 D1 E0 D0 SC
Flag bits
*
Oscillator selection
Driving wave form
E.V.R. register set
Display
Oscillator selection EXOSC 0 1
Oscillator circuit External resistor and capacitor External oscillation signal input
*
Driving waveform WSEL Driving waveform 0 A(Time sharing system frequency) waveform 1 B(Flame reversal) waveform Driving waveform is chosen according to the characteristic of a panel.
*
E.V.R. resister set E.V.R. resistor set instruction adjusts the contrast of the LCD, by 3-bits selects(E2,E1,E0). One LCD driving voltage VLCD out of 8 voltage-stages by setting E.V.R. register. Set the binary code "000" when contrast adjustment is unused. V1 E2 E1 E0 VLCD (V0~VSS ) 1/2bias 1/3bias 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 V0 0.933V 0 0.875V 0 0.824V 0 0.778V 0 0.737V 0 0.700V 0 0.667V 0 V0 0.955V 0 0.913V 0 0.875V 0 0.840V 0 0.808V 0 0.778V 0 0.750V 0 High : : : : : : Low
Ver.2008-11-28
-7-
NJU6543
*
Preliminary
Display ON/OFF OFF ON
Display ON/OFF SC 0 1
When Display OFF * All segment and common terminal output VSS (When general purpose output ports are selected, even Display OFF, these ports can output data) * Suspending Oscillation (but, if RSTb="L", oscillator works) * V1 , V2 and V3 become "H" (no current pass through the bleeder resistors) Even during Display OFF, interface can be accessed, and data can be written into the command register, address counter and data register. (5) Output Address Counter Output Address Counter will specify the addresses of the SEG and COM drivers for the display data. st When the MSB (D7 to D6) of the 1 data is "01", the LSB 6 bits (D5 to D0) specify the addresses of COM and nd st SEG drivers, and the 2 data is the display data which will be sent to the 1 -data-specified drivers. At the same time, SEG and COM driver addresses will be increased automatically shown in Table 1. In other words, as of the SEG and COM driver addresses specified by the first data in the Output Address Counter, display data can be transferred to the SEG and COM drivers without further address setting. The address setting range is from "000000" to "111111". if the data transferred additionally , then it will be reset to "000000" and renew the auto-increment operation.
*
Address Data D7 0
D6 1
D5 C1
D4 C0
D3 S3
D2 S2
D1 S1
D0 S0
Flag bits
COM driver Address
SEG driver Address
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Ver.2008-11-28
Preliminary
C1 0 C0 0 S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 COM Driver COM1 SEG Driver D4 D3 SEG4 SEG5 SEG12 SEG13 SEG20 SEG21 SEG28 SEG29 SEG36 SEG37 SEG44 SEG45 SEG52 SEG53 SEG60 SEG61 SEG68 SEG69 SEG76 SEG77 SEG84 SEG85 SEG92 SEG93 SEG100 SEG101 SEG108 SEG109 SEG116 SEG117 SEG124 SEG125 SEG4 SEG5 SEG12 SEG13 SEG20 SEG21 SEG28 SEG29 SEG36 SEG37 SEG44 SEG45 SEG52 SEG53 SEG60 SEG61 SEG68 SEG69 SEG76 SEG77 SEG84 SEG85 SEG92 SEG93 SEG100 SEG101 SEG108 SEG109 SEG116 SEG117 SEG124 SEG125 SEG4 SEG5 SEG12 SEG13 SEG20 SEG21 SEG28 SEG29 SEG36 SEG37 SEG44 SEG45 SEG52 SEG53 SEG60 SEG61 SEG68 SEG69 SEG76 SEG77 SEG84 SEG85 SEG92 SEG93 SEG100 SEG101 SEG108 SEG109 SEG116 SEG117 SEG124 SEG125 SEG4 SEG5 SEG12 SEG13 SEG20 SEG21 SEG28 SEG29 SEG36 SEG37 SEG44 SEG45 SEG52 SEG53 SEG60 SEG61 SEG68 SEG69 SEG76 SEG77 SEG84 SEG85 SEG92 SEG93 SEG100 SEG101 SEG108 SEG109 SEG116 SEG117 SEG124 SEG125
NJU6543
Table 1. The Relationship Between Output Address and SEG/COM Drivers
D7 SEG1 SEG9 SEG17 SEG25 SEG33 SEG41 SEG49 SEG57 SEG65 SEG73 SEG81 SEG89 SEG97 SEG105 SEG113 SEG121 SEG1 SEG9 SEG17 SEG25 SEG33 SEG41 SEG49 SEG57 SEG65 SEG73 SEG81 SEG89 SEG97 SEG105 SEG113 SEG121 SEG1 SEG9 SEG17 SEG25 SEG33 SEG41 SEG49 SEG57 SEG65 SEG73 SEG81 SEG89 SEG97 SEG105 SEG113 SEG121 SEG1 SEG9 SEG17 SEG25 SEG33 SEG41 SEG49 SEG57 SEG65 SEG73 SEG81 SEG89 SEG97 SEG105 SEG113 SEG121 D6 SEG2 SEG10 SEG18 SEG26 SEG34 SEG42 SEG50 SEG58 SEG66 SEG74 SEG82 SEG90 SEG98 SEG106 SEG114 SEG122 SEG2 SEG10 SEG18 SEG26 SEG34 SEG42 SEG50 SEG58 SEG66 SEG74 SEG82 SEG90 SEG98 SEG106 SEG114 SEG122 SEG2 SEG10 SEG18 SEG26 SEG34 SEG42 SEG50 SEG58 SEG66 SEG74 SEG82 SEG90 SEG98 SEG106 SEG114 SEG122 SEG2 SEG10 SEG18 SEG26 SEG34 SEG42 SEG50 SEG58 SEG66 SEG74 SEG82 SEG90 SEG98 SEG106 SEG114 SEG122 D5 SEG3 SEG11 SEG19 SEG27 SEG35 SEG43 SEG51 SEG59 SEG67 SEG75 SEG83 SEG91 SEG99 SEG107 SEG115 SEG123 SEG3 SEG11 SEG19 SEG27 SEG35 SEG43 SEG51 SEG59 SEG67 SEG75 SEG83 SEG91 SEG99 SEG107 SEG115 SEG123 SEG3 SEG11 SEG19 SEG27 SEG35 SEG43 SEG51 SEG59 SEG67 SEG75 SEG83 SEG91 SEG99 SEG107 SEG115 SEG123 SEG3 SEG11 SEG19 SEG27 SEG35 SEG43 SEG51 SEG59 SEG67 SEG75 SEG83 SEG91 SEG99 SEG107 SEG115 SEG123 D2 SEG6 SEG14 SEG22 SEG30 SEG38 SEG46 SEG54 SEG62 SEG70 SEG78 SEG86 SEG94 SEG102 SEG110 SEG118 SEG126 SEG6 SEG14 SEG22 SEG30 SEG38 SEG46 SEG54 SEG62 SEG70 SEG78 SEG86 SEG94 SEG102 SEG110 SEG118 SEG126 SEG6 SEG14 SEG22 SEG30 SEG38 SEG46 SEG54 SEG62 SEG70 SEG78 SEG86 SEG94 SEG102 SEG110 SEG118 SEG126 SEG6 SEG14 SEG22 SEG30 SEG38 SEG46 SEG54 SEG62 SEG70 SEG78 SEG86 SEG94 SEG102 SEG110 SEG118 SEG126 D1 SEG7 SEG15 SEG23 SEG31 SEG39 SEG47 SEG55 SEG63 SEG71 SEG79 SEG87 SEG95 SEG103 SEG111 SEG119 SEG127 SEG7 SEG15 SEG23 SEG31 SEG39 SEG47 SEG55 SEG63 SEG71 SEG79 SEG87 SEG95 SEG103 SEG111 SEG119 SEG127 SEG7 SEG15 SEG23 SEG31 SEG39 SEG47 SEG55 SEG63 SEG71 SEG79 SEG87 SEG95 SEG103 SEG111 SEG119 SEG127 SEG7 SEG15 SEG23 SEG31 SEG39 SEG47 SEG55 SEG63 SEG71 SEG79 SEG87 SEG95 SEG103 SEG111 SEG119 SEG127 D0 SEG8 SEG16 SEG24 SEG32 SEG40 SEG48 SEG56 SEG64 SEG72 SEG80 SEG88 SEG96 SEG104 SEG112 SEG120 SEG128 SEG8 SEG16 SEG24 SEG32 SEG40 SEG48 SEG56 SEG64 SEG72 SEG80 SEG88 SEG96 SEG104 SEG112 SEG120 SEG128 SEG8 SEG16 SEG24 SEG32 SEG40 SEG48 SEG56 SEG64 SEG72 SEG80 SEG88 SEG96 SEG104 SEG112 SEG120 SEG128 SEG8 SEG16 SEG24 SEG32 SEG40 SEG48 SEG56 SEG64 SEG72 SEG80 SEG88 SEG96 SEG104 SEG112 SEG120 SEG128
0
1
COM2
Increment Direction
1
0
COM3
1
1
COM4
! !
If general purpose ports are selected by Command Register, under (C1, C0, S3, S2, S1, S0)=(0, 0, 1, 1, 1, 1), D0 ~ D4 bits are the addresses of (P1, P2, P3,P4) ports which corresponds to (SEG125,SEG126, SEG127, SEG128). When SEG125~SEG128 are set as general purpose output ports, data for SEG125~SEG128 during COM2~COM4 scanning will be ignored.
Ver.2008-11-28
-9-
NJU6543
Preliminary
(6) Power ON Reset After power ON, NJU6543 is initialized to the following values: * Address counter (C1, C0, S3, S2, S1, S0)=(0, 0, 0, 0, 0, 0) * Display data register all "0" * Duty ratio 1/4 duty * Bias ratio 1/3 bias * Oscillator selection External resistor and capacitor * Driving waveform A waveform * E.V.R. resister V0(E2, E1, E0)=(0, 0, 0) * Segment/General purpose port: Segment output(SEG125,SEG126, SEG127, SEG128) * Display OFF (7) Sequence of Initialization (7-1)1/4 duty,1/3 bias,SEG125 ~ SEG128 used as SEG drivers, external resister and capacitor, A waveform,E.V.R. V0(E2, E1, E0)=(0, 0, 0) data written in from COM1. Power on D7 1 D7 1 D7 0 D6 1 D6 0 D6 1 D5 0 D5 0 D5 0 D4 0 D4 0 D4 0 D3 0 D3 0 D3 0 D2 0 D2 0 D2 0 D1 0 D1 0 D1 0 D0 0 D0 0 D0 0 External R&C,A waveform V0(E2, E1, E0)=(0, 0, 0) Pixels off 1/4 duty 1/3 Bias Segment port COM driver address =00 SEG driver address=0000
Set Command Resister2
Set Command Register1
Set output address
Display data written in D7 D6 1 1 D5 0 D4 0 D3 0 D2 0 D1 D0 0 1 Pixels on
Set Command Register2
(7-2)1/3 duty,1/2 bias,SEG128 used as general purpose ports, external oscillation signal input, B waveform,E.V.R. V0(E2, E1, E0)=(1, 1, 1) data written in from COM2. Power on D7 1 D7 1 D7 0 D6 1 D6 0 D6 1 D5 1 D5 0 D5 0 D4 1 D4 1 D4 1 D3 1 D3 1 D3 0 D2 1 D2 0 D2 0 D1 1 D1 0 D1 0 D0 0 D0 1 D0 0 External signal, B waveform V0(E2, E1, E0)=(1, 1, 1) Pixels off 1/3 duty 1/2 Bias SEG128 general ports COM driver address =01 SEG driver address=0000
Set Command Resister2
Set Command Register1
Set output address
Display data written in D7 D6 1 1 D5 1 D4 1 D3 1 D2 1 D1 D0 1 1 Pixels on
Set Command Register2
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Ver.2008-11-28
Preliminary
NJU6543
(8-1) LCD driving voltage generation circuit LCD driving voltage generation circuit generates LCD driving bias voltages V1 , V2 and V3. It adjusts the voltage by 8 steps electrical volume from V0 and allots the voltage to V0, V1 , V2 and V3 by resistor-voltage-dividing as shown in below. V0, V1, V2 and V3 terminals requires external capacitors for bias voltage stabilization for display quality. These values of capacitors should be fixed in accordance with evaluation in the application.
NJU6543 internal V0
E.V.R.(8 steps)
V1 V2
4kOhm 4kOhm 4kOhm
VLCD
V3 4kOhm VSS
When the E.V.R. is not used, V1 terminal should connect to V0. When the NJU6543 operates as 1/2 bias operation, V2 terminal should connect to V3.
(8-2) Oscillator circuit The oscillator consists of an external capacitor and an resistor It generates clock signal for LCD driving. When use external clock, input the clock signal to OSC. VDD
390kOhm
NJU6543
OSC 120pF
(fOSC=14.5kHz TYP)
Ver.2008-11-28
- 11 -
NJU6543
Preliminary
! ABSOLUTE MAXIMAM RATINGS
PARAMETER Supply Voltage 1 Supply Voltage 2 Supply Voltage 3 Input Voltage Operating Temp. Storage Temp. Dissipation Power Note-1) SYMBOL VDD V0 V1, V2, V3 VIN Topr Tstg PD RATINGS -0.3 ~ +7.0 -0.3 ~ +7.0 -0.3 ~ V0+0.3 -0.3 ~ VDD+0.3 -40 ~ +105 -55 ~ +125 1000 UNIT V V V V C C mW (VSS=0V, Ta=25C) CONDITIONS
INHb, CSb, SCK, SI, RSTb, OSC applicable.
Note-2) Note-3) Note-4)
The power dissipation is value mounted on 4 layer glass epoxy board in size 76.2mm x 114.3mm x 1.6tmm Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also recommended that the IC be used within the range specified in the DC electrical characteristics, or the electrical stress may cause mulfunctions and impact on the reliability. All voltages are relative to VSS = 0V reference. The following relationship shall be maintained. V0 V1 V2 V3 VSS, V0 VDD, and V0 shall be input after VDD. To stabilize the LSI operation, place decoupling capacitors between VDD-VSS and between V0-VSS.
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Ver.2008-11-28
Preliminary
! ELECTRICAL CHARACTERISTICS
*
NJU6543
DC characteristics 1 (VDD=2.4 to 3.6V, VSS=0V, Ta=-40 to 105C) PARAMETER
Power Supply LCD Driving Voltage LCD Bias Voltage "H" Level Input Voltage "L" Level Input Voltage Hysteresis Voltage "H" Level Input Current "L" Level Input Current "H" Level Output Voltage "L" Level Output Voltage Driver-on Resistance (COM) Driver-on Resistance (SEG) Oscillating Frequency External Clock Frequency External Clock Duty Bleeder Resistor E.V.R
SYM BOL
VDD V0 V2 V3 VIH VIL VH IIH IIL VOH VOL RCOM RSEG fOSC fCP duty RB REVR IDD1 IDD2
CONDITIONS V0 VDD
Ta=25C Testing via COM/SEG terminals COM/SEG without load CSb, SCK, SI, RESb, OSC CSb, SCK, SI, RESb, OSC CSb, SCK, SI, RESb VIN= VDD CSb, SCK, SI, RESb VIN= VSS CSb, SCK, SI, RESb VDD =3V, IO=5mA, P1 to P4 VDD =3V, IO=5mA, P1 to P4 Id=1A, VLCD=3V/5.5V Id=1A, VLCD=3V/5.5V VDD =3V, ROSC=390kOhm, Cosc=120pF, Ta=25C Input into OSC Input into OSC VLCD-VSS Ta=25C V0-V1 Ta=25C E.V.R.=V0(1,1,1) VDD =3V, Display off Ta=25C VDD =3V, VLCD=5V, Ta=25C, Checker flag display, 1/3 bias Using external R & C, no output VDD=3V, VLCD=5V, Display off Ta=25C VDD =3V, VLCD=5V, Ta=25C, Checker flag display, 1/3 bias no output, E.V.R.=(1,1,1)
MIN
2.4 2.4 2/3 V1-0.2 1/3 V1-0.2 0.8 VDD 0
TYP
MAX
3.6 6.0
UNIT V V V V V V V A A V
Not e
2/3 V1 1/3 V1
2/3 V1+0.2 1/3 V1+0.2 VDD 0.2 VDD
0.2VDD 1.0 1.0 VDD-0.6 0.6 12.6 45 9 3 3 15.4 50 12 4 4 10 10 18.2 55 15 5 5 10 90 1 320 450
V kOhm kOhm kHz kHz % kOhm
kOhm
5 5
A A A A
Operating Current ILCD1 ILCD2
Note-5) Driver-On resistance (RSEG/RCOM) is measured from V0, VSS, V1 , V2 or V3 terminal to each SEG/COM terminal when Id current flows through COM/SEG terminals. Note-6) ["H" Level Input Voltage], ["L" Level Input Voltage], [Hysteresis Voltage], ["H" Level Input Current], ["L" Level Input Current], [External Clock Frequency] and [External Clock Duty] are as the same as if VDD=4.5 to 5.5V.
Ver.2008-11-28
- 13 -
NJU6543
*
Preliminary
(VDD=4.5 to 5.5V, VSS=0V, Ta=-40 to 105C) SYM BOL
VDD VLCD V2 V3
DC characteristics 2 PARAMETER
Power Supply LCD Driving Voltage LCD Bias Voltage "H" Level Input Voltage "L" Level Input Voltage Hysteresis Voltage "H" Level Input Current "L" Level Input Current "H" Level Output Voltage "L" Level Output Voltage Driver-on Resistance (COM) Driver-on Resistance (SEG) Oscillating Frequency External Clock Frequency External Clock Duty Bleeder Resistor E.V.R
CONDITIONS V0 VDD
Ta=25C Testing via COM/SEG terminals COM/SEG without load CSb, SCK, SI, RESb, OSC CSb, SCK, SI, RESb, OSC CSb, SCK, SI, RESb VIN= VDD CSb, SCK, SI, RESb VIN= VSS CSb, SCK, SI, RESb VDD =5V, IO=10mA, P1 to P4 VDD =5V, IO=10mA, P1 to P4 Id=1A, VLCD=4.5V/5.5V Id=1A, VLCD=4.5V/5.5V VDD =3V, ROSC=390kOhm, Cosc=120pF, Ta=25C Input into OSC Input into OSC V1-VSS Ta=25C V0-V1 Ta=25C E.V.R.=V0(1,1,1) VDD =5V, Display off, Ta=25C VDD =5V, Ta=25C, Checker flag display, 1/3 bias Using external R & C, no output VDD =5V, V0=5V,Display off, Ta=25C VDD =5V, V0=5V, Ta=25C, Checker flag display, 1/3 bias Using external R & C, no output E.V.R.=Vo(1,1,1)
MIN
4.5 4.5 2/3 V1-0.2 1/3 V1-0.2 0.8VDD 0
TYP
MAX
5.5 6.0
UNIT
V V V V V V V A A V
Not e
2/3 V1 1/3 V1
2/3 V1+0.2 2/3 V1+0.2 VDD 0.2 VDD
VIH VIL VH IIH IIL VOH VOL RCOM RSEG fOSC fCP duty RB REVR IDD1 IDD2
0.2VDD 1.0 1.0 VDD-1.0 1.0 12.6 12.6 45 9 3 15.4 15.4 50 12 4 10 10 18.2 18.2 55 15 5 12.5 130 1
V kOhm kOhm kHz kHz % kOhm kOhm A A A A 7 7
Operating Current
ILCD1
ILCD2
320
450
Note-7) Driver-On resistance (RSEG/RCOM) is measured from V0, VSS, V1 , V2 or V3 terminal to each SEG/COM terminal when Id current flows through COM/SEG terminals. Note-8) ["H" Level Input Voltage], ["L" Level Input Voltage], [Hysteresis Voltage], ["H" Level Input Current], ["L" Level Input Current], [External Clock Frequency] and [External Clock Duty] are as the same as if VDD=2.4 to 3.6V.
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Ver.2008-11-28
Preliminary
*
NJU6543
AC characteristics
(VDD=VLCD=2.4 to 5.5V, VSS=0V, Ta=-40 to 105C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Note "L" Level Clock Pulse Width tWCLL 230 ns "H" Level Clock Pulse tWCLH 230 ns Width Data Setup Time tDS 20 ns Data Hold Time tDH 20 ns CSb Wait Time tCP 50 ns 9 CSb Setup Time tCS 180 ns CSb Hold Time tCH 50 ns CSb"H" Level Pulse Width tWCH 50 ns Rising Time tr 20 ns Falling Time tf 20 ns Note-9) tCP is the time when SCK is kept at "H" during CSb changed from "H" to "L".
*
Input Timing tWCH CSb tCP tCS VIL VIL tDS SI tDH tWCLH tWCLL tf tr tCH
SCK
*
Input condition when hardware reset circuit is used PARAMETER Reset Input "L" Level Width Reset Rising Time Reset Falling Time SYMBOL tRSL trRS tfRS tfRS VIH RSTb VIL CONDITIONS fOSC= 15.4kHz MIN 1.5 TYP MAX (Ta=25C) UNIT ms 100 ns 100 ns
tRSL
trRS
*
Power supply condition when hardware reset circuit is used PARAMETER Power-on Rising Time Power-off Time SYMBOL trDD tOFF 2.2V VDD 0.2V 0.2V CONDITIONS MIN 0.1 1 (Ta=-40 to 105C) TYP MAX UNIT 5 ms ms
trDD tOFF Note 10) tOFF is the off time when power-supply turns off suddenly or cycles on/off.
Ver.2008-11-28
- 15 -
NJU6543
Preliminary
fosc/192(Hz)
V1
! LCD DRIVING WAVEFORM
1/2 duty, 1/2 bias, A waveform
COM1
V2,V3 VSS
COM2
V1 V2,V3 VSS V1 V2,V3 VSS
COM3
COM4
V1 V2,V3 VSS
"OFF" segment output correspond to COM1 and 2.
V1 V2,V3 VSS
"ON" segment output correspond to COM1.
V1 V2,V3 VSS
"ON" segment output correspond to COM2.
V1 V2,V3 VSS
"ON" segment output correspond to COM1 and 2.
V1 V2,V3 VSS
- 16 -
Ver.2008-11-28
Preliminary
1/2duty, 1/3bias, Awaveform fosc/192(Hz)
NJU6543
COM1
V1 V2 V3 VSS
COM2
V1 V2 V3 VSS
COM3
V1 V2 V3 VSS V1 V2 V3 VSS
COM4
"OFF" segment output correspond to COM1 and 2.
V1 V2 V3 VSS
"ON" segment output correspond to COM1.
V1 V2 V3 VSS
"ON" segment output correspond to COM2
V1 V2 V3 VSS
"ON" segment output correspond to COM1 and 2
V1 V2 V3 VSS
Ver.2008-11-28
- 17 -
NJU6543
Preliminary
fosc/192(Hz)
V1 V2,V3 VSS
1/3duty, 1/2bias, Awaveform
COM1
COM2
V1 V2,V3 VSS
COM3
V1 V2,V3 VSS
COM4
V1 V2,V3 VSS
"OFF" segment output correspond to COM1, 2, and 3.
V1 V2,V3 VSS
"ON" segment output correspond to COM1.
V1 V2,V3 VSS
"ON" segment output correspond to COM2.
V1 V2,V3 VSS
"ON" segment output correspond to COM1 and 2.
V1 V2,V3 VSS
"ON" segment output correspond to COM3.
V1 V2,V3 VSS
"ON" segment output correspond to COM1 and 3.
V1 V2,V3 VSS
"ON" segment output correspond to COM2 and 3.
V1 V2,V3 VSS
"ON" segment output correspond to COM1, 2 and 3.
V1 V2,V3 VSS
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Ver.2008-11-28
Preliminary
1/3duty, 1/3bias, Awaveform fosc/192(Hz)
NJU6543
COM1
V1 V2 V3 VSS
COM2
V1 V2 V3 VSS
COM3
V1 V2 V3 VSS
COM4
V1 V2 V3 VSS
"OFF" segment output correspond to COM1, 2 and 3.
V1 V2 V3 VSS V1 V2 V3 VSS
"ON" segment output correspond to COM1.
"ON" segment output correspond to COM2.
V1 V2 V3 VSS
"ON" segment output correspond to COM1 and 2.
V1 V2 V3 VSS
"ON" segment output correspond to COM3.
V1 V2 V3 VSS V1 V2 V3 VSS
"ON" segment output correspond to COM1 and 3.
"ON" segment output correspond to COM2 and 3.
V1 V2 V3 VSS
"ON" segment output correspond to COM1, 2 and 3.
V1 V2 V3 VSS
Ver.2008-11-28
- 19 -
NJU6543
Preliminary
fosc/192(Hz)
V1 V2,V3 VSS V1 V2,V3 VSS
1/4duty, 1/2bias, A waveform COM1
COM2
COM3
V1 V2,V3 VSS
COM4
V1 V2,V3 VSS
"OFF" segment output correspond to COM1, 2, 3 and 4.
V1 V2,V3 VSS
"ON" segment output correspond to COM1. "ON" segment output correspond to COM2. "ON" segment output correspond to COM1 and 2. "ON" segment output correspond to COM3. "ON" segment output correspond to COM1 and 3. "ON" segment output correspond to COM2 and 3. "ON" segment output correspond to COM1, 2 and 3 "ON" segment output correspond to COM4. "ON" segment output correspond to COM2 and 4 "ON" segment output correspond to COM1, 2, 3 and 4.
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
- 20 -
Ver.2008-11-28
Preliminary
1/4duty, 1/3bias, A waveform COM1 fosc/192(Hz)
NJU6543
V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS
COM2
COM3
COM4
"OFF" segment output correspond to COM1, 2, 3 and 4 "ON" segment output correspond to COM1. "ON" segment output correspond to COM2. "ON" segment output correspond to COM1 and 2. "ON" segment output correspond to COM3. "ON" segment output correspond to COM1 and 3. "ON" segment output correspond to COM2 and 3. "ON" segment output correspond to COM1, 2 and 3. "ON" segment output correspond to COM4. "ON" segment output correspond to COM2 and 4. "ON" segment output correspond to COM1, 2, 3 and 4.
Ver.2008-11-28
- 21 -
NJU6543
Preliminary
fosc/192(Hz)
V1 V2,V3 VSS
1/2duty, 1/2bias, B waveform
COM1
COM2
V1 V2,V3 VSS V1 V2,V3 VSS
COM3
COM4
V1 V2,V3 VSS
"OFF" segment output correspond to COM1 and 2
V1 V2,V3 VSS
"ON" segment output correspond to COM1.
V1 V2,V3 VSS
"ON" segment output correspond to COM2.
V1 V2,V3 VSS
"ON" segment output correspond to COM1 and 2.
V1 V2,V3 VSS
- 22 -
Ver.2008-11-28
Preliminary
1/2duty, 1/3bias,B waveform fosc/192(Hz)
NJU6543
COM1
V1 V2 V3 VSS
COM2
V1 V2 V3 VSS
COM3
V1 V2 V3 VSS
COM4
V1 V2 V3 VSS
"OFF" segment output correspond to COM1 and 2.
V1 V2 V3 VSS
"ON" segment output correspond to COM1.
V1 V2 V3 VSS V1 V2 V3 VSS
"ON" segment output correspond to COM2.
"ON" segment output correspond to COM1 and 2
V1 V2 V3 VSS
Ver.2008-11-28
- 23 -
NJU6543
Preliminary
fosc/192(Hz)
1/3duty, 1/2bias, B waveform
COM1
V1 V2,V3 VSS
COM2
V1 V2,V3 VSS
COM3
V1 V2,V3 VSS
COM4
V1 V2,V3 VSS
"OFF" segment output correspond to COM1, 2, and 3.
V1 V2,V3 VSS
"ON" segment output correspond to COM1.
V1 V2,V3 VSS
"ON" segment output correspond to COM2.
V1 V2,V3 VSS
"ON" segment output correspond to COM1 and 2.
V1 V2,V3 VSS
"ON" segment output correspond to COM3.
V1 V2,V3 VSS
"ON" segment output correspond to COM1 and 3.
V1 V2,V3 VSS
"ON" segment output correspond to COM2 and 3.
V1 V2,V3 VSS
"ON" segment output correspond to COM1, 2 and 3.
V1 V2,V3 VSS
- 24 -
Ver.2008-11-28
Preliminary
1/3duty, 1/3bias, B waveform fosc/192(Hz)
NJU6543
COM1
V1 V2 V3 VSS
COM2
V1 V2 V3 VSS V1 V2 V3 VSS
COM3
COM4
V1 V2 V3 VSS
"OFF" segment output correspond to COM1, 2 and 3.
V1 V2 V3 VSS
"ON" segment output correspond to COM1.
V1 V2 V3 VSS
"ON" segment output correspond to COM2.
V1 V2 V3 VSS
"ON" segment output correspond to COM1 and 2.
V1 V2 V3 VSS
"ON" segment output correspond to COM3.
V1 V2 V3 VSS
"ON" segment output correspond to COM1 and 3.
V1 V2 V3 VSS
"ON" segment output correspond to COM2 and 3.
V1 V2 V3 VSS
"ON" segment output correspond to COM1, 2 and 3.
V1 V2 V3 VSS
Ver.2008-11-28
- 25 -
NJU6543
Preliminary
fosc/192(Hz)
V1 V2,V3 VSS
1/4duty, 1/2bias, B waveform COM1
COM2
V1 V2,V3 VSS
COM3
V1 V2,V3 VSS
COM4
V1 V2,V3 VSS
"OFF" segment output correspond to COM1, 2, 3 and 4.
V1 V2,V3 VSS
"ON" segment output correspond to COM1. "ON" segment output correspond to COM2. "ON" segment output correspond to COM1 and 2. "ON" segment output correspond to COM3. "ON" segment output correspond to COM1 and 3. "ON" segment output correspond to COM2 and 3. "ON" segment output correspond to COM1, 2 and 3. "ON" segment output correspond to COM4. "ON" segment output correspond to COM2 and 4. "ON" segment output correspond to COM1, 2, 3 and 4.
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
V1 V2,V3 VSS
- 26 -
Ver.2008-11-28
Preliminary
1/4duty, 1/3bias, B waveform COM1 fosc/192(Hz)
NJU6543
V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS
COM2
COM3
COM4
"OFF" segment output correspond to COM1, 2, 3 and 4.
"ON" segment output correspond to COM1. "ON" segment output correspond to COM2. "ON" segment output correspond to COM1 and 2. "ON" segment output correspond to COM3. "ON" segment output correspond to COM1 and 3. "ON" segment output correspond to COM2 and 3. "ON" segment output correspond to COM1, 2 and 3. "ON" segment output correspond to COM4. "ON" segment output correspond to COM2 and 4. "ON" segment output correspond to COM1, 2, 3 and 4.
Ver.2008-11-28
- 27 -
NJU6543
#
Preliminary
Input and Output terminal structure
VDD
VDD
IN
IN
VSS
VSS
RSTb, TEST, CSb, SI,SCK
OSC
VDD VDD V0 V0 OUT VDD V0 V0 VDD VDD OUT
VSS
SEG1~SEG124, COM1~COM4
SEG125/P1~SEG128/P4
- 28 -
Ver.2008-11-28
Preliminary
! APPLICATION CIRCUIT
* 1/4 duty, 1/3 bias V0
NJU6543
V0 VDD V1 V2 V3
SEG1
VDD
SEG128/P4
NJU6543
VSS
VSS COM1 COM2 COM3 COM4
From MCU
RSTb CSb SCK SI
LCD Panel
OSC
* 1/4
duty, 1/2 bias V0 VDD V1 V2 V3 SEG128/P4 SEG1
V0 VDD
NJU6543
VSS
VSS RSTb COM1 COM2 COM3 COM4
From MCU
CSb SCK SI
LCD Panel
OSC
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
Ver.2008-11-28
- 29 -

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